The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Non-volatile memory devices include an array of memory cells that store information. The memory cells are non-volatile in that they can retain the stored information even when not powered. Examples of non-volatile memory devices include read-only memory (ROM), flash memory, computer storage devices, such as hard disk drives, and optical disc drives.
Non-volatile memory devices may include multi-bit cell configurations. For some multi-bit cell configurations, each memory cell may have more than one storage region and each storage region may store one or more bits of data.
Referring now to FIG. 1, an exemplary memory cell 102 includes a transistor having a substrate 103, control gate 104 and a charge storage region 106. The substrate 103 may have a first region 105a, which may include a source or a drain, and a second region 105b, which may include a source or a drain. The charge storage region 106 may include a floating gate, an insulated layer, or various other configurations. Electrons that are placed on the charge storage region 106 may be trapped there because the charge storage region 106 is electrically isolated from the control gate 104 by an insulating layer (not shown). Multi-level cell configurations may be created by storing various quantities of charge on the charge storage region.
Referring now to FIG. 2, a block diagram of an exemplary memory system 113 is shown. The memory system 113 includes an array 107 of memory cells 102, a bit line decoder 116, a word line decoder 118, and a control module 120. The array 107 includes M rows and N columns of (M*N) memory cells 102. The bit line decoder 116 selects one of N columns of memory cells 102 via bit lines 108. The word line decoder 118 selects one of M rows of memory cells 102 via word lines 112.
The control module 120 may include an address control module 122 and a read/write (R/W) control module 124. The address control module 122 may control addressing of the memory cells 102 via the bit line decoder 116 and the word line decoder 118. The R/W control module 124 may control R/W operations of the memory cells 102 via the bit line decoder 116 and the word line decoder 118.
The R/W control module 124 may execute a read cycle to access data stored in the memory cells 102. During each read cycle, the R/W control module 124 may access memory cells 102 by applying voltages to the control gates 104 via the corresponding word lines 112. Each of the voltages may correspond to a different storage region. For example, during a first read cycle, the R/W control module 124 may read the data in the first storage region 105a in a memory cell. In a second read cycle, the R/W control module 124 may read the data in a second storage region 105b in a memory cell. The R/W control module 124 may read out contents of the storage regions as binary codes that represent stored data.